; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-w64-windows-gnu | FileCheck %s

%union.c_v256.26.65.104.143.962.1248 = type { [4 x i64] }

define void @_ZN14simd_test_avx216c_imm_v256_alignILi1EEE6c_v256S1_S1_(ptr byval(%union.c_v256.26.65.104.143.962.1248) align 4) #0 {
; CHECK-LABEL: _ZN14simd_test_avx216c_imm_v256_alignILi1EEE6c_v256S1_S1_:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmovdqu {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT:    vpsllq $56, %ymm0, %ymm0
; CHECK-NEXT:    vmovdqu %ymm0, (%eax)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retl
entry:
  %b.sroa.0.sroa.2.0.b.sroa.0.0..sroa_cast.sroa_idx38 = getelementptr inbounds %union.c_v256.26.65.104.143.962.1248, ptr %0, i32 0, i32 0, i32 1
  %1 = load <2 x i64>, ptr %b.sroa.0.sroa.2.0.b.sroa.0.0..sroa_cast.sroa_idx38, align 4
  %b.sroa.0.sroa.4.0.copyload = load i64, ptr undef, align 4
  %2 = extractelement <2 x i64> %1, i32 0
  %3 = extractelement <2 x i64> %1, i32 1
  %4 = insertelement <4 x i64> undef, i64 %2, i32 0
  %5 = insertelement <4 x i64> %4, i64 %3, i32 1
  %6 = insertelement <4 x i64> %5, i64 %b.sroa.0.sroa.4.0.copyload, i32 2
  %7 = insertelement <4 x i64> %6, i64 undef, i32 3
  %8 = shl <4 x i64> %7, <i64 56, i64 56, i64 56, i64 56>
  %9 = or <4 x i64> %8, zeroinitializer
  store <4 x i64> %9, ptr undef, align 8
  ret void
}

attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+avx,+avx2,+cx8,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "unsafe-fp-math"="false" "use-soft-float"="false" }

